1. Field of the Invention
The present invention relates to an image display device and method for displaying images by sequentially sampling image signals being inputted for a display screen having an aspect ratio of X:Y.
2. Description of the Related Art
Display devices typified by liquid crystal display devices have advantages in being thin, lightweight, and having lower power consumption. By making use of, these features, they are used as display devices for personal computers and word processors and as display devices for TVs and car navigation systems. Furthermore, they are used as projection displays. In this way, they are used in various applications. Among. others, active matrix liquid crystal display devices (AMLCDS) including display screens having display pixels arranged in rows and columns, each of which pixel is electrically connected with switching elements, can realize good image quality without crosstalk between adjacent pixels. Because of these features, active matrix liquid crystal display devices are being earnestly investigated and developed. In recent years, the aspect ratio of the display screen has shifted from 4:3 to 16:9 at which the image is elongated in the direction of horizontal scanning and which permits visual perception of a large-sized screen.
Where an image signal such as a TV signal having information about 4:3 aspect ratio picture is displayed on a liquid crystal display device having a display screen with an aspect ratio of 16:9, it is common practice to sample a previously image-processed picture signal at successive points by an image-processing technique using a frame memory or the like, and then the image is displayed.
FIG. 4 is a block diagram schematically showing the configuration of the prior art image display device. For example, this device has an input processing circuit 1 that is composed of a demodulator circuit 103, a matrix circuit 104, and an analog-to-digital converter circuit 105 as shown in FIG. 5. An image signal is applied via input terminals 101 and 102 and demodulated into brightness signals Y1, Y2, chrominance signals C1, C2, and synchronizing signals S1, S2 by the demodulator circuit 103. Then, the matrix circuit 104 demodulates three primary signals R1, G1, B1; R2, G2, and B2 from the brightness signals Y1, Y2 and the chrominance signals C1, C2. The three primary color signals R1, G1, B1; R2, G2, B2 and synchronizing signals S1, S2 are applied to the A/D converter circuit 105, which converts the input signals into digital form, or image signals VD1 and VD2. These image signals VD1 and VD2 are supplied to a frame synchronizer circuit 2 shown in FIG. 1.
As shown in FIG. 6, the frame synchronizer circuit 2 consists of a control circuit 201 and a frame memory 202. The control circuit 201 controls reading and writing of the image signal VD2 to and from the frame memory 202 in response to the synchronizing signals S1 and S2 supplied to the control circuit 201. The image signals VD1 and VD2, which are synchronized to each other on frame period, are supplied to a data converter circuit 3 shown in FIG. 4.
The data converter circuit 3 converts data about the image signals VD1, VD2 into data adapted for image display on the liquid crystal display device 7 and sends the data to an image synthesizer circuit 5. A remaining area signal generator circuit 4 produces a remaining area signal that is supplied to the liquid crystal display device 7 except for the effective image display period for the liquid crystal display device 7. The image synthesizer circuit 5 produces a combination of the remaining area signal and an image signal produced from the data converter circuit 3. The synthesized image signal from the image synthesizer circuit 5 is sent to an output processing circuit 6. This output processing circuit 6 performs various kinds of processing, such as digital-to-analog conversion, gamma correction, and polarity switching, to convert the signal to a signal adapted for the liquid crystal display device 7.
As shown in FIG. 7, the liquid crystal display device 7 comprises a liquid crystal panel 701, four X-driver circuits 703-1, 703-2, 703-3, 703-4 electrically connected with the liquid crystal panel 701, a Y-driver circuit 704 for supplying scanning pulses for display panel, and a control circuit portion 705. The four X-driver circuits 703-1, 703-2, 703-3, and 703-4 sample an image signal to thereby supply a desired voltage for display panel.
Although not illustrated in the figure, the liquid crystal panel 701 has a layer of a twisted-nematic liquid crystal sandwiched between an array substrate and a counter substrate via orientation films. A sealing material makes these components stationary relative to each other. Polarizing plates are mounted on the outer surfaces of the substrates such that their axes of polarization are mutually perpendicular to each other. As an example, 320xc3x973 signal lines Xi (i=1, 2, . . . , 960) and 240 scanning lines Yj (j=1, 2, . . . , 240) are arranged to extend perpendicularly to each other. Pixel electrodes consisting of indium-tin oxide (ITO) are arranged near the intersections of the signal lines Xi and scanning lines Yj via inverted-staggered thin-film transistors (TFTs). These TFTs comprise a thin film of amorphous silicon as an active layer. Auxiliary capacitor lines Cj (j=1, 2, . . . , 240) extending parallel to the scanning lines Yj are arranged on the array substrate. These auxiliary capacitor lines have regions overlapping with the pixel electrodes. The pixel electrodes and the auxiliary capacitor lines Cj form auxiliary capacitors (CS) at the pixels.
The counter substrate has layers of color filters (not shown) of three primary colors red (R), green (G), and blue (B) that are positioned between matrix light-shielding layers (not shown) to achieve color display. One of the light-shielding layers acts to shield gaps among the TFTs formed on the array substrate, the signal lines Xi, and the pixel electrodes. The other light-shielding layer serves to shield the gaps between the scanning lines Yj and the pixel electrodes. Furthermore, a counter electrode consisting of ITO as described above is located on the counter substrate.
The control circuit portion 705 of the liquid crystal panel 701 supplies a horizontal clock signal (XCK), a horizontal start signal (XST), and image signals to the X-driver circuits 703-1, 703-2, 703-3, and 703-4 and produces a vertical clock signal YCK and a vertical start signal YST to the Y-driver circuit 704.
One example of the data converter circuit 8 is shown in FIG. 8. One form of display provided by the liquid crystal display device 7 is shown in FIGS. 9A-9D. The structure of the data converter circuit 8 is described in detail by referring to FIGS. 8 and 9A-9D. The data converter circuit 8 comprises 1H memory circuits 301, 302, 310, writing control circuits 303, 311, reading control circuits 304, 312, selector circuits 305, 306, 307, 308, and a digital filter 309.
It is assumed that the liquid crystal display device 701 uses a display screen 702 with an aspect ratio of 16:9 as shown in FIG. 9A. The selector circuit 307 of the data conversion circuit 3 supplies that of the image signals VD1 and VD2 selected by the selector circuit 306 to the image synthesizer circuit 5. The image signal supplied in this way is displayed on the viewing screen with an aspect ratio of 16:9 during an effective display period that is 80% of the horizontal scanning period of 1 H. In consequence, a display in the form shown in FIG. 9A is provided.
Then, the display screen 702 is divided into display areas A and B with an aspect ratio of 9:8 as shown in FIG. 9B. Image signals are displayed on these display areas. In response to the input synchronizing signal S1 and clock signal, the writing control circuit 303 thins out the data about the two image signals VD1 and VD2 into half and writes the thinned out data into the 1 H memory circuits 301 and 302, the image signals VD1 and VD2 being synchronized to the frame and supplied from the frame synchronizing circuit 2.
In response to the input synchronizing signal S1 and clock signal, the reading control circuit 304 reads the whole data from the 1 H memory circuits 301 and 302 in a xc2xd H period. The selector circuit 307 causes the image signals read from the 1 H memory circuits 301 and 302 to be selectively passed through the selector circuit 305 and thus the time-shared, multiplexed image signals are supplied to the image synthesizer circuit 5. The supplied signals are displayed on the viewing screen with an aspect ratio of 16:9 during an effective display period that is 80% of the 1 H horizontal scanning period. Consequently, the image signals VD1 and VD2 or the image signals VD2 and VD1 can be displayed on the display areas A and B, respectively, shown in FIG. 9B.
It is assumed that the display screen 702 is divided into a first display area A and a second display area B with aspect ratios of 12:9 (4:3) and 9:4, respectively, as shown in FIG. 9C or 9D. An image signal is displayed on the area A, while a remaining area signal is displayed on the area B.
The selector circuit 308 of the data converter circuit 3 supplies either one of the input image signals VD1 and VD2 to the digital filter 309. This digital filter 309 interpolates the image signal supplied via the selector circuit 308, based on an interpolation operating control signal supplied from the writing control circuit 311, on an interpolation clock signal, and on the clock signal described above, so that three data items of the image signal are derived from every four data items inputted from the selector circuit 308 and then supplied to the 1 H memory circuit 310. The writing control circuit 311 writes the output signal from the digital filter 309 into the 1 H memory circuit 310 in response to the interpolation clock signal. In response to the input synchronizing signal S1 and clock signal, the reading control circuit 312 is clocked to read out all the data written with the interpolation clock signal.
The selector circuit 307 receives the image signal from the 1 H memory circuit 310 and sends it to the image synthesizer circuit 5. This image synthesizer circuit 5 receives an image signal from the data conversion circuit 3 that has been compressed on the time axis (on time base) to xc2xe of the effective display period, which effective display period is 80% of the 1 H horizontal scanning period of the image signal. Also, the data conversion circuit 3 receives the remaining area signal from the remaining area signal generator circuit 4 that is supplied during the remaining period that is xc2xc of the effective display period. The image synthesizer circuit 5 produces the combination of these two input signals and output to the output processing circuit 6. Since the image in the effective display period is displayed on the viewing screen with the aspect ratio of 16:9, the image signal and the remaining area signal can be displayed on the areas A and B, respectively, shown in FIGS. 9C and 9D.
In the prior art technique described above, the data converter circuit 3 is made complex in configuration to divide the display screen, horizontally into equal or unequal picture areas with various aspect ratios, such as 12:9, 9:4, 9:8 when an aspect ratio of the display screen is 16:9. The selector circuit 306 is necessary to display the image signal on the display screen with an aspect ratio of 16:9. The 1 H memory circuits 301 and 302 are needed to display the image signal on a pair of image areas with an aspect ratio of 9:8. Furthermore, the writing control circuit 303, the reading control circuit 304, and the selector circuits 305, 307 are necessitated. In addition, in order to display the image display on areas having arbitrary aspect ratios such as 12:9 and 9:4, it is necessary to provide the selector circuit 308, the digital filter 309, the 1 H memory circuit 310, the writing control circuit 311, and the reading control circuit 312.
That is, at least the three circuit systems corresponding to three aspect ratios of the displayed images need to be added. This complicates the structure of the data converter circuit 3. Especially, the circuit of the writing control circuit 311 that produces the interpolation operating control signal and the interpolation clock signal are rendered complex. Furthermore, in order that the function of the digital filter 309 acting to thin out data in writing data about the image signal into the 1 H memory circuit 310 correspond to any desired aspect ratio, plural kinds of circuits must be used in combination to realize plural kinds of filter functions. This increases the size of the digital filter 309, thus leading to an increase in the cost of the image display device.
It is an object of the present invention to provide an improved image display device that has a simplified structure but is capable of appropriately displaying image signals on image display areas with arbitrary aspect ratios.
A certain image display device sequentially samples inputted image signals and thereby displays images on display screen having an aspect ratio of X:Y. In accordance with the present invention, the image display device comprises an image signal synthesizer means for synthesizing for producing a synthesized image signal derived from at least one of the inputted image signals during each horizontal scanning period; a clock frequency control means for producing frequency-controlled clock signals each in accordance with respective one of horizontal display area size ratios Z/Y and (Yxe2x88x92Z)/Y, when to divide said display screen into a first area having an aspect ratio of X:Z (Z less than Y) and a second area having an aspect ratio of X:(Yxe2x88x92Z); and a display control means for sampling each image signal in the synthesized image signal by respective one of said frequency-controlled clock signals and thereby displaying images on said first and second areas.
In one embodiment of the invention, the image display device is further equipped with a signal compression means for compressing the inputted image signal on the time axis and sending the compressed signal to the image signal synthesizer means described above.
In another embodiment of the invention, the aforementioned signal compression means comprises a storage means for storing the image signal, a writing control means for writing the image signal into the storage means, and a reading control means for reading out the image signal at a rate faster than the writing rate.
In a further embodiment of the invention, the aspect ratio of the first area is 9:8 while the aspect ratio of the display screen is 16:9.
In a yet other embodiment of the invention, the aspect ratio of the first area is 12:9 while the aspect ratio of the display screen is 16:9.
In the configuration in accordance with the present invention described thus far, the image signal synthesizer means produces a synthesized image signal derived from at least one of the inputted image signals during each horizontal scanning period. The clock frequency control means controls frequencies of clock signals to produce frequency-controlled clock signals each in accordance with respective one of horizontal display area size ratios Z/Y and (Yxe2x88x92Z)/Y, when to divide said display screen into a first area having an aspect ratio of X:Z (Z less than Y) and a second area having an aspect ratio of X:(Yxe2x88x92Z). The display control means samples each image signal in the synthesized image signal by respective one of said frequency-controlled clock signals. Because the image signal to be displayed on the first area is sampled with the sampling clock signal that is controlled according to the horizontal display area size ratio Z/Y, the image signal is appropriately displayed on the first area. On the other hand, because the image signal to be displayed on the second area is sampled with a sampling clock signal that is controlled according to the horizontal display portion size ratio (Yxe2x88x92Z)/Y, the image signal is appropriately displayed on the second area.
In this way, image signals can be appropriately displayed on display areas having an arbitrary horizontal size ratio by causing the clock frequency control means to control frequencies of clock signals each in accordance with respective one of horizontal display area size ratios Z/Y and (Yxe2x88x92Z)/Y. This makes it unnecessary to prepare plural kinds of circuits corresponding to different aspect ratios of display areas. Hence, the circuit configuration can be simplified. Furthermore, image signals can be appropriately displayed on display areas with any arbitrary aspect ratio.
Where the display device in accordance with the present invention is equipped with the signal compression means for compressing the inputted image signal on the time axis and sending it to the image signal synthesizer means, if the image signal is compressed to 1/m of one horizontal scanning period, the sampling clock signals are controlled according to the horizontal display portion size ratio Z/Y or (Yxe2x88x92Z)/Y and also according to the compression ratio 1/m described above. Consequently, where a synthesized image signal from the image synthesizer means is displayed, the synthesized image signal can be sampled over one horizontal period. Hence, an appropriate display can be accomplished. Thus, the same advantages as described above can be obtained.
Where the above-described signal compression means of the device in accordance with the invention comprises the storage means for storing the image signal, the writing control means for writing the image signal into the storage means, and the reading control means for reading out the image signal at a rate faster than the writing rate, the aforementioned compression of the image signal along the time axis is achieved. Therefore, the aforementioned advantages can be realized.
Where the display screen has an aspect ratio of 16:9 and the first area has an aspect ratio of 9:8 or 12:9, the sampling clock signals are controlled with X=9, Y=16, and Z=8 or Z=12. In this case, it is obvious that the aforementioned advantages can be had.
Other objects and features of the invention will appear in the course of the description thereof, which follows.